Address scrambling in a semiconductor memory

Abstract

A semiconductor memory includes a memory array and an address scrambler. The address scrambler maps sequential input addresses to non-sequential physical addresses for the memory array. In one embodiment, the address scramble includes circuitry that implements a one-to-one function mapping of the logical addresses to physical addresses. Alternatively, the address scrambler includes a pseudo-random series generator that generates a pseudo-random series for the physical addresses. In either case, consecutive memory accesses that would logically correspond to a single row or column are scattered among multiple rows and columns to diminish the length of a gap in a data sequence that would otherwise occur as a result of a defective row or column. For flash memory, the mapping can be restricted so that logical addresses for a sector map to physical address for the same or another sector. The scrambler optionally includes a volatile storage for a key or access code that selects the mapping or series used for determining the physical addresses. The access code used when recording must also be used during playback or the correct data will not be accessed.